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 LeCroy, Testing The Future
Advances in measurement techniques make the task of troubleshooting power supply designs systematic and precise. Neil Reynolds, product manager at Aspen Electronics, discusses three powerful techniques for rapidly characterising and debugging switching-mode power supply designs.
Applications include ensuring the voltage transition edge rate and range of frequency of power supply switching cycles, plus monitoring duty cycle variation from the controller IC. So in this article I will outline these real-world engineering challenges and provide a practical solution for each. Switching-mode power supply designers can immediately begin implementing these solutions with real-time oscilloscope tools using the described techniques.
 Figure 1: WaveScan identifies and highlights six switching cycles with instantaneous frequencies outside of the frequency stability region. A zoom of one of the anomalous cycles is automatically highlighted in red in the lower grid
Stability
Frequency stability of switching cycles: Identifying frequency stability problems within a switching-mode power supply (SMPS) can be greatly simplified when using an automated method. When an oscilloscope detects the period of a waveform cycle, this value can be directly inverted to compute the instantaneous frequency of the specific waveform cycle. Using all-instance measurements, instead of considering only the value of one cycle within the acquired waveform, the series of instantaneous frequencies of each cycle of an entire acquired input waveform can be computed as an array.
With a tolerance band applied to instantaneous frequencies, the array of continuous instantaneous frequencies can be scanned by the oscilloscope to detect anomalous frequency content on a per-cycle basis. The waveform scanning technique incorporates this new approach and can report frequency anomalies graphically and numerically to identify all switching cycles which are outside of frequency stability margins requirements.
In Figure 1, a SMPS power transistor's drain-to-source voltage is probed differentially on Channel 1. In this case, the threshold level of the frequency measurement parameter is set at 20% of the waveform amplitude level to allow for the frequency-at-level measurement to include the switching frequency only and to exclude any higher frequency oscillations. The user should visually inspect the waveform to determine the appropriate threshold level setting. For waveforms with oscillations within the period, the threshold level should be increased or decreased to include rising edges of the primary switching cycle only.
The scanning filter limit is set to the nominal instantaneous cycle frequency of 66.04 kHz, with a 50 Hz delta defining the frequency tolerance band. Triggering action of the resultant scan of frequency is set to save waveform data when the frequency stability margin is exceeded. The oscilloscope has displayed a red box encompassing each entire waveform cycle which violates the defined scan tolerance band, and six cycles from the power supply have failed to meet this criteria.
 Figure 2: WaveScan identifies power supply switching transition failures and accumulates a distribution of all 1000 failures in the red histogram. The green histicon contains a distribution of all 10,000 measured SMPS switching transitions.
Voltage transition
Power transistor drain-to-source voltage transition time for power supply device turn-off: The drain-to-source voltage of the switching MOSFET approaches zero during conduction and approaches the upper voltage rail during non-conduction. The voltage transition times correspond to device turn-on and turn-off transition periods. An SMPS drain-to-source voltage transition can be determined from a single rise time measurement for device turn-off, and from a single full-time measurement for device turn-on. However, to ensure accurate device behaviour, a single rise-time or full-time measurement will not suffice. Statistically, a sample population of over 1000 corresponds to a ±3-sigma measurement confidence, and a sample population of 10,000 corresponds to over ±3.5- sigma measurement confidence.
In Figure 2, a +±3.5-sigma level of measurement confidence of drain-to-source voltage transition time has been obtained. Using all-instance measurements of rise-time, the green histicon (iconic histogram) shows a statistically significant rise-time measurement population of over 10,956 rise-time measurements. Of the 10,956 measurements accumulated in the measurement histicon, waveform scanning has identified 1635 transitions which did not meet the user-defined measurement criteria for turn-off voltage transitions. All values which meet the scanning criteria have been logged into the red histogram. This technique can also be used to verify power supply device turn-on compliance by substituting fall-time in place of rise-time in the scan criteria.
In this case, the five most recent rise-time anomalies are listed in a tabular index in the upper-left edge of the display, and these correspond to the five red areas highlighted in the Channel 1 waveform trace. Clicking on any of the index numbers will highlight that specific rise-time violation in bright yellow. In addition, the Z1 zoom trace corresponds to the selected rise-time anomaly. The red scan histogram contains the entire distribution of drain-to-source voltage transition failures as designated by user defined criteria. Waveform data is automatically saved each time an anomaly is detected.
The histogram distribution can quickly identify modulation characteristics. Figure 2 showed a Gaussian histogram distribution which contained one main mode, with rise-time values clustered around the mean, and randomly distributed out to the tails. This distribution shape indicates random noise on the rise-time measurement, which is due to the electrical noise generated by any electrical circuit. By contrast, the red histogram shown in Figure 3 has two main modes in the histogram, or a bimodal distribution.
The rise-time measurements are clustered around two main modes and randomly distributed around the modes. In this case, there is a large number of rise-time measurements clustered around the (rightmost) approximately 105ns rise-time measurement mode, and a more sparse distribution of rise-time measurements clustered around the minor (leftmost) 90ns mode. Between the two clusters of rise-time measurements, there are virtually no rise-time measurement values falling into the range of 95-100 ns.
The lack of data in this range indicates that a source of modulation such as crosstalk, coupling, or oscillator effects are causing the rise-time value to modulate back and forth between the two main modes. The method of analysing power supply characteristics using scanning histograms provides insight which can help to rapidly identify the source of the problem in the SMPS.
 Figure 3: The red WaveScan ScanHisto distribution shows a bimodal distribution of rise-time. The histogram shape indicates that a source of modulation is affecting the power supply turn-off transition stability.
Signal output
Proper gate-drive signal output: In order to analyse the control loop response of a power supply, the differential voltage between the gate and source of the power transistor is measured. The controller IC responds to load changes by varying the pulse widths. The gate-drive signal from the controller IC contains these varying pulse widths, which determines how long the device remains in the on state. The widths become narrower when the load is turned off. Waveform scanning of duty cycle through the waveform will identify waveform pulses whose duty cycle parametric values drop below a user-defined threshold. Use of waveform scanning for duty cycle is used to identify gate-drive failures which occur while the power supply has reached regulation.
By contrast, scanning for duty cycle during a load change can be used to identify key timing areas in which the MOSFET is reacting to reduce power supply voltage at the output corresponding to the change in load. The duty cycle values located in the scan can either be anomalies, identifiers for indicating proper operation timing, or both, depending on the application context.
Scan overlay mode allows for duty cycles meeting user-defined criteria to be shown in a persistent display. The overlaid pulses need not occur from separate acquisitions. Adjacent pulses from within the same single waveform acquisition can be shown in an overlaid display, provided that they meet the user-defined criteria for scan identification.
Figure 4 shows an actual device in which a power supply load changes from maximum to minimum load. All of the duty cycle values below the threshold are highlighted in red, and the scan overlay shows a persistent mapping of all of the narrow pulses corresponding to the user-defined criteria of duty cycles with values of less than 5%.
 Figure 4: WaveScan identifies (highlighted in red) all controller IC pulses whose duty cycles are less than 5%. Shown in the blue trace is a persistent overlay of all pulses whose duty cycle values meet this criteria.
Fast and efficient
Waveform scanning makes debugging a circuit fast and efficient. Automatic scans can monitor for pulses under steady load, drifts in frequency, widths that are too narrow, intermittent events, and many other phenomena as shown within the three applications above.
When operating on multiple acquisitions, the tool continuously scans and executes actions based on user-defined criteria. When a power supply design challenge is described in terms of a timing measurement, then waveform scanning techniques rapidly find anomalous conditions. Measurement filtering methods are available to further narrow the search criteria. The ability to view histogrammed and overlaid measurement and data values provides further analysis of the anomalies identified by the scan.
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